1. Field of Invention
The present invention relates to auto-stopping slurry compositions for polishing topographic dielectric silicon dioxide film layers and a method of planarizing topographic dielectric silicon dioxide film layers using the same.
2. Description of Related Art
One of the primary applications for chemical-mechanical polishing (“CMP”) in integrated circuit (“IC”) fabrication is the planarization of topographic dielectric silicon dioxide film layers (e.g., to form inter-level dielectric (“ILD”) layers and as a first step in shallow trench isolation (“STI”) processing). For purposes of illustration, the ILD CMP process is schematically depicted in FIGS. 1-3.
FIG. 1 shows a side sectional view of a portion of an IC device 10 prior to ILD layer formation. The IC device 10 includes a plurality of features 20 formed on a dielectric substrate 30, which is typically elemental silicon or a previously formed ILD layer. In the illustrated embodiment, the features 20 (which are also sometimes referred to in the art as device elements) are metal wires. It will be appreciated that other features such as resistors, capacitors, transistors, etc. will typically be present in an IC device. Although all of the features 20 shown in FIGS. 1-3 are of the same height above the dielectric substrate 30, it will be appreciated that various features will often be of different height in actual IC devices.
FIG. 2 shows the next step of the process of forming an ILD layer in which the features 20 and dielectric substrate 30 have been covered with a dielectric silicon dioxide film 40, which is typically formed via a chemical vapor deposition (“CVD-SiO2”) process. It will be appreciated that the dielectric silicon dioxide layer 40 can be formed by other processes The dielectric silicon dioxide film 40 covers both the features 20 and the dielectric substrate 30, thereby generally duplicating their surface topography. Thus, the top surface of the dielectric silicon dioxide film 40 is “topographic”, meaning that the top surface of the dielectric silicon dioxide film includes both elevated up areas 50 and recessed down areas 60.
FIG. 3 shows the IC device 10 after ILD CMP. Ideally, the up areas 50 have been removed at a substantially greater removal rate than the down areas 60 during ILD CMP, thereby producing a substantially planar surface 70 on which additional features can be formed. Preferably, the post-ILD CMP dielectric silicon dioxide film layer 40 exhibits a substantially uniform and desired thickness.
The conventional ILD CMP process does not utilize a stop layer to prevent over-polishing of the dielectric silicon dioxide film. The conventional ILD CMP process utilizes endpoint detection techniques or predetermined fixed-time polishing techniques to determine when to stop polishing. Both of these polishing stop techniques can produce non-uniformities across the polished silicon dioxide surface due to within-die topography variations and/or within-wafer polishing rate variations. In addition, over-polishing, meaning polishing beyond the end point, tends to rapidly remove the dielectric silicon dioxide film layer thereby disadvantageously thinning the resultant ILD layer.